DocumentCode :
936209
Title :
Safety property verification using sequential SAT and bounded model checking
Author :
Parthasarathy, Ganapathy ; Iyer, Madhu K. ; Cheng, Kwang-Ting Tim ; Wang, Li-C
Author_Institution :
California Univ., Santa Barbara, CA, USA
Volume :
21
Issue :
2
fYear :
2004
Firstpage :
132
Lastpage :
143
Abstract :
Model checkers verify properties of safety- or business-critical systems. The main idea behind model checking is to convert a design´s verification into a problem of checking key design properties expressed as a set of temporal logic formulas. The graph representing the design´s state space then becomes the basis for testing these formulas´ satisfiability (SAT). This divide-and-conquer approach provides an overall test for design correctness. We describe a method for checking safety properties using sequential SAT. SSAT can efficiently prove true properties by harnessing the power of bounded model checking (BMC) using SAT, but without the need for a pre-computed correctness threshold. Using a standard set of benchmarks, we conducted experiments to compare the runtime behavior of SSAT with BMC and binary decision diagrams (BDDs).
Keywords :
computability; computational complexity; divide and conquer methods; formal verification; sequential circuits; temporal logic; tree searching; benchmarks; binary decision diagrams; bounded model checking; computational complexity; divide-and-conquer method; safety property verification; satisfiability; search algorithms; sequential SAT; sequential circuits; Automata; Boolean functions; Data structures; Explosions; Helium; Law; Legal factors; Logic design; Safety;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2004.1277906
Filename :
1277906
Link To Document :
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