A doughnut layout style for improved switching speed with CMOS VLSI gates

Author

Longway, Charles ; Siferd, Raymond

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

Volume

24

Issue

1

fYear

1989

Firstpage

194

Lastpage

198

Abstract

A doughnut style for physical layout of CMOS gates which improves the switching speed of the gates compared to a standard layout style is discussed. This improvement in performance is obtained by decreasing the self-loading output capacitance for a given W/L ratio of the transistor channels. A design for a 30-bit incrementer which was fabricated and tested as a 3- mu m VLSI circuit is included as an example of an application for the doughnut-style gates. The incrementer has a propagation delay of less than 10 ns through nine stages of logic gates with large fan-outs at three of the stages.<>

Keywords

CMOS integrated circuits; VLSI; circuit layout; integrated circuit technology; logic design; 10 ns; 3 micron; CMOS VLSI gates; CMOS gates; VLSI circuit; W/L ratio; doughnut layout style; doughnut-style gates; example; improvement in performance; large fan-outs; load capacitance reduction; output capacitance; physical layout; propagation delay; switching speed; Capacitance; Insulation; Permittivity; Propagation delay; Rough surfaces; Surface roughness; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.16324

Filename

16324