Jitter analysis of a phase-locked digital timing recovery system

An analytical approach is presented for the jitter performance of a timing recovery circuit consisting of a hard-limiter, an exclusive-or gate, followed by a second-order phase-locked loop. Exact expressions for the autocorrelation function and the power spectral density of the zero-crossing jitter in the data signal are derived, and then the phase jitter variance of the timing wave, generated at the output of the timing circuit, is obtained analytically as a function of various system parameters. Finally, numerical results and a comparative performance analysis show that considerable improvement can be achieved in jitter performance in addition to having the advantage of low cost and simple hardware implementation.<>