A method for consistent fault coverage reporting

Author

Debany, Warren H., Jr. ; Kwiat, Kevin A. ; Al-Arian, Sami A.

Author_Institution

Rome Lab., Griffiss Air Force Base, NY, USA

Volume

10

Issue

3

fYear

1993

Firstpage

68

Lastpage

79

Abstract

Procedure 5012 of Mil-Std-883, which describes requirements for the logic model, the assumed fault model and universe, fault classing, fault simulation and reporting of test results for digital microcircuits is described. The procedure provides a consistent means of measuring fault coverage regardless of the specific logic and fault simulator used. Procedure 5012 addresses complex, embedded structures such as random-access memories (RAMs), read-only memories (ROMs), and programmable logic arrays (PLAs) weighting gate-level and non-gate-level structures by transistor counts to arrive at overall fault coverage.<>

Keywords

fault location; integrated circuit testing; integrated memory circuits; logic arrays; logic testing; random-access storage; read-only storage; standards; Mil-Std-883; PLAs; RAMs; ROMs; consistent fault coverage reporting; digital microcircuits; embedded structures; fault classing; fault coverage; fault model; fault simulation; fault simulator; logic model; procedure 5012; programmable logic arrays; random-access memories; read-only memories; transistor counts; weighting gate-level; Circuit faults; Circuit testing; Laboratories; Logic devices; Logic testing; Manufacturing; Mathematical model; Predictive models; Quality assessment; System testing;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/54.232474

Filename

232474