A new route to zero-barrier metal source/drain MOSFETs

Author

Connelly, Daniel ; Faulkner, Carl ; Grupp, D.E. ; Harris, J.S.

Author_Institution

Acorn Technol., Palo Alto, CA, USA

Volume

3

Issue

1

fYear

2004

fDate

3/1/2004 12:00:00 AM

Firstpage

98

Lastpage

104

Abstract

A new method for dramatically lowering the Schottky barrier resistance at a metal/Si interface by interposing an ultrathin insulator is demonstrated for the first time, with thermionic barriers less than those reported to date with silicides. Results with Er and near-monolayer thermal SiN_x at the interface are consistent with simulations of effective metal Fermi level separations from the silicon conduction band of 0.15 V for n-type Si and 45 mV for p-type Si. Simulations of advanced metal source/drain (S/D) ultrathin-body CMOS devices in comparison with competitive doped S/D devices show a significant performance advantage with a barrier to the conduction band of up to 0.1 V.

Keywords

CMOS logic circuits; Fermi level; MOSFET; Schottky barriers; conduction bands; elemental semiconductors; erbium; insulators; semiconductor-metal boundaries; silicon; silicon compounds; CMOS devices; Er-Si-SiN; Fermi level; Schottky barrier resistance; conduction band; metal/Si interface; monolayer thermal SiN_x compounds; thermionic barriers; ultrathin insulator; zero-barrier metal drain MOSFET; zero-barrier metal source MOSFET; CMOS technology; Contact resistance; Erbium; Insulation; MOSFETs; Metal-insulator structures; Silicides; Silicon compounds; Silicon on insulator technology; Voltage;

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2003.820774

Filename

1278276