Test generation for digital circuits described by means of register transfer languages

In this paper, we propose systematic procedures for generating the test sequence for digital systems described by means of procedural register transfer languages. Faults in the data unit (data faults) and in the control unit (control faults) will require different techniques for their detection. For the data unit, a graph representing the data flow, the transfer graph, is proposed. Techniques for justifying and sensitising data faults are described. For the control unit we study the problem of its identification by using distinguishing sequences for its states. Testing of both units can be overlapped to reduce the length of the test sequence for the whole circuit.