DocumentCode
938239
Title
Hierarchical multiprocessor architecture
Author
Morris, D. ; Theaker, C.J.
Author_Institution
University of Manchester Institute of Science and Technology, Department of Computation, Manchester, UK
Volume
134
Issue
4
fYear
1987
fDate
7/1/1987 12:00:00 AM
Firstpage
161
Lastpage
167
Abstract
The paper is concerned with a multiprocessor computer architecture, which offers a flexible and high-performance system at low cost. The processing elements in the design may be connected as a hierarchy, and the system software supports a virtual memory which may be distributed throughout the processing elements. The principal form of communication is therefore through shared data structures. The paper examines the design of this memory system and considers two approaches for using the architecture, namely as a conventional process-based system and as a dataflow system.
Keywords
parallel architectures; storage management; virtual storage; MC68010; MC68451; VME bus cluster; data driven task scheduling; dataflow system; memory system design; multiprocessor computer architecture; process-based system; shared data structures; system software; virtual memory;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
DOI
10.1049/ip-e.1987.0031
Filename
4647119
Link To Document