Analysis of input and output configurations for use in four-valued CCD programmable logic arrays

As in binary, a multiple-valued programmable logic array (PLA) realises a sum-ofproducts expression specified by the user. However, in multiple-valued logic, there are many more operations than in binary, and an important question is the choice of operations which provides the greatest number of functions for a given chip area. In this paper, we analyse various PLA configurations using operations realised in the peristaltic multiple-valued CCD technology. We compare a multiple-valued CCD PLA implementation with four other proposed designs and show that there is a significant difference in chip area required to realise the same set of functions. The basis of comparison is the set of 4-valued unary functions.