DocumentCode :
938297
Title :
Efficient bit-level systolic array for the linear discriminant function classifier
Author :
Wang, C.-L. ; Wei, C.-H. ; Chen, S.-H.
Author_Institution :
National Chiao Tung University, Institute of Electronics, Hsinchu, Republic of China
Volume :
134
Issue :
5
fYear :
1987
fDate :
10/1/1987 12:00:00 AM
Firstpage :
216
Lastpage :
224
Abstract :
The linear discriminant function classifier is a widely used but computationally demanding method in statistical pattern recognition. This paper describes a bit-level systolic array for the linear discriminant function classifier to improve its processing speed. The system includes a new scheme for inner product computation, which not only has 100% efficiency but also gains a speed improvement over a previous method, and yields classification results at an average rate of one per B cycles of the array, where B is the wordlength of the input data. The throughput is higher than those of the related bit level arrays described previously.
Keywords :
cellular arrays; computerised pattern recognition; digital arithmetic; parallel architectures; 100 percent; bit-level systolic arrays; inner product computation; linear discriminant function classifier; parallel processing; speed improvement; statistical pattern recognition;
fLanguage :
English
Journal_Title :
Electronic Circuits and Systems, IEE Proceedings G
Publisher :
iet
ISSN :
0143-7089
Type :
jour
DOI :
10.1049/ip-g-1:19870032
Filename :
4647124
Link To Document :
بازگشت