Title :
A 50-mW/ch 2.5-gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking
Author :
Liu, Yangfan ; Yum, Tsz Yin ; Xue, Quan ; Chan, Chi Hou
Author_Institution :
Wireless Commun. Res. Centre, City Univ. of Hong Kong, Kowloon, China
fDate :
3/1/2004 12:00:00 AM
Abstract :
Typical frequency doublers achieve high conversion gain by reflecting back the 2nd harmonic to the input port of the active device through a quarter-wave open-circuited stub. In this paper, a S-band frequency doubler with a 12 dB conversion gain outperforms the conventional design by 5 dB, after replacing the conventional stub with a Compact Microstrip Resonant Cell (CMRC). The CMRC serves as suitable terminations for both the 2nd and 3rd harmonics to enhance the desired output power of the 2nd harmonic, while appearing as a good pass-band for the fundamental frequency.
Keywords :
circuit layout CAD; circuit optimisation; digital phase locked loops; system buses; timing jitter; SFI-5 interface; circuit area minimization; digital data recovery circuit; digital eye-tracking; digital-PLL-type DR circuit design; high-frequency jitter; long-term wander tracking; multibit interfaces; power consumption minimizaztion; Frequency conversion; Microstrip; Microwave circuits; Power generation; Power harmonic filters; Power system harmonics; Reflection; Resonance; Scattering parameters; Wireless communication;
Journal_Title :
Microwave and Wireless Components Letters, IEEE
DOI :
10.1109/LMWC.2004.825179
