New pipelined vector-reduction arithmetic unit for FIR filter implementation

In realising an N-tap finite impulseresponse (FIR) filter, N multiplications and N ¿¿ 1 additions must be performed during every sampling interval. The multiplication process can be pipelined easily because there is no recurrence. The (N ¿¿ l)-port addition process is essentially a vector-reduction process with inherent recurrence and is a bottleneck of hardware utilisation when implemented using a pipelined arithmetic unit. In the paper we present a new pipeline structure for implementing the multiport adder. For an arithmetic pipeline with M segments, our new design achieves the theoretical upper bound on hardware utilisation provided that N ¿¿ (L + 2)M ¿¿ 2L+1 where L = Int (log2(M)), the largest integer less than or equal to log2(M). This pipeline structure is also useful in pipelined signal-processor design.