• DocumentCode
    938698
  • Title

    Pipeline prime-factor DFT for VLSI using cyclic shuffling

  • Author

    Shyu, H.C. ; Truong, T.K. ; Reed, I.S. ; Hsu, I.S.

  • Author_Institution
    University of Southern California, Department of Electrical Engineering, Los Angeles, USA
  • Volume
    134
  • Issue
    5
  • fYear
    1987
  • fDate
    9/1/1987 12:00:00 AM
  • Firstpage
    247
  • Lastpage
    253
  • Abstract
    The fast prime-factor discrete Fouriertransform (DFT) algorithm [2¿¿4] can be used to reduce the number of basic cells when the transform length of a DFT is not a highly composite number. This pipeline prime-factor DFT can be realised by a one-to r-dimensional index mapping by (r ¿¿ 1) one-to two-dimensional mappings. Hence, only the one-to two-dimensional shuffling algorithm is needed to realise a practical prime-factor DFT. Recently, it was shown that a new algorithm can be developed to perform the shuffling operations needed in implement the above-mentioned one-to two-dimensional mapping for a prime-factor DFT. In the paper, the new shuffling algorithm is established and proved for the general case. It is evident that this algorithm can be applied directly to many different implementations of the prime-factor DFT, including a pipeline VLSI implementation.
  • Keywords
    Fourier transforms; VLSI; matrix algebra; ( r-1) one- to two-dimensional mappings; basic cells; cyclic shuffling; fast prime-factor discrete Fourier-transform algorithm; mathematical techniques; matrix algebra; one- to r-dimensional index mapping; one- to two-dimensional shuffling algorithm; pipeline VLSI implementation; pipeline prime-factor DFT; transform length;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings E
  • Publisher
    iet
  • ISSN
    0143-7062
  • Type

    jour

  • DOI
    10.1049/ip-e.1987.0041
  • Filename
    4647162