DocumentCode :
938850
Title :
Niagara: a 32-way multithreaded Sparc processor
Author :
Kongetira, Poonacha ; Aingaran, Kathirgamar ; Olukotun, Kunle
Author_Institution :
Sun MicroSystems Inc., Sunnyvale, CA, USA
Volume :
25
Issue :
2
fYear :
2005
Firstpage :
21
Lastpage :
29
Abstract :
The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. This is an entirely new implementation of the Sparc V9 architectural specification, which exploits large amounts of on-chip parallelism to provide high throughput. The hardware supports 32 threads with a memory subsystem consisting of an on-board crossbar, level-2 cache, and memory controllers for a highly integrated design that exploits the thread-level parallelism inherent to server applications, while targeting low levels of power consumption.
Keywords :
cache storage; instruction sets; multi-threading; multiprocessing systems; parallel architectures; pipeline processing; Niagara; Sparc V9 architectural specification; commercial server application; memory controllers; multithreaded Sparc processor; on-board crossbar; on-chip parallelism; Application software; Bandwidth; Clocks; Costs; Enterprise resource planning; Foot; Frequency; Hardware; Power supplies; Yarn; Microprocessors and microcomputers; Multithreaded processors; Shared memory;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/MM.2005.35
Filename :
1453485
Link To Document :
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