Alternative iterative digital multiplier based on cellular arrays of r.o.m.s

An alternative and even more economical iterative-array-multiplier design is presented using only half the number of r.o.m.s each half the size as our earlier version. It is shown to perform simple multiply operations with one-third saving in computation time. Thus, with a 30 ns clock, 48×48 bit multiplication takes 2.88 ¿s.