Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package

Embedded passives are gaining in importance due to the reduction in size of electronic products. Capacitors pose the biggest challenge for integration in packages due to the large capacitance required for decoupling high performance circuits. Surface mount discrete (SMD) capacitors become ineffective charge providers above 100 MHz due to the increased effect of loop inductance. This paper focuses on the importance of embedded capacitors above this frequency. Modeling, measurements, and model to hardware correlation of these capacitors are shown. Design and modeling of embedded capacitor arrays for decoupling processors in the midfrequency band (100 MHz-2 GHz) is also highlighted in this paper.