Title :
Porosity-aware buffered Steiner tree construction
Author :
Alpert, Charles J. ; Gandham, Gopal ; Hrkic, Milos ; Hu, Jiang ; Quay, Stephen T. ; Sze, C.N.
Author_Institution :
IBM Corp., Austin, TX, USA
fDate :
4/1/2004 12:00:00 AM
Abstract :
In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis system. Modern designs may contain large blocks which severely constrain the buffer locations. Even when there may appear to be space for buffers in the alleys between large blocks, these regions are often densely packed or may be needed later to fix critical paths. Therefore, within physical synthesis, a buffer insertion scheme needs to be aware of the porosity of the existing layout to be able to decide when to insert buffers in dense regions to achieve critical performance improvement and when to utilize the sparser regions of the chip. This work addresses the problem of finding porosity-aware buffering solutions by constructing a "smart Steiner tree" to pass to van Ginneken\´s topology-based algorithm. This flow allows one to fully integrate the algorithm into a physical synthesis system without paying an exorbitant runtime penalty. We show that significant improvements on timing closure are obtained when this approach is integrated into a physical synthesis system.
Keywords :
VLSI; circuit layout CAD; integrated circuit design; integrated circuit interconnections; integrated circuit layout; trees (mathematics); IC design; VLSI; buffer insertion; fast placer implementation; fine granularity clustering; global placer; net absorption; physical synthesis system; placement algorithms; porosity-aware buffered Steiner tree construction; van Ginneken topology-based algorithm; very large scale integration; wire-length prediction; Circuit synthesis; Dynamic programming; Integrated circuit interconnections; Integrated circuit synthesis; Integrated circuit technology; Runtime; Steiner trees; Timing; Topology; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2004.825864