DocumentCode :
940587
Title :
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
Author :
Xiang, Dong ; Chen, Mingjing ; Fujiwara, Hideo
Author_Institution :
Tsinghua Univ. Beijing, Beijing
Volume :
56
Issue :
12
fYear :
2007
Firstpage :
1619
Lastpage :
1628
Abstract :
The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.
Keywords :
built-in self test; flip-flops; logic testing; BIST; clock cycle; scan flip-flops; scan-based built-in self-test; test vector; testability estimation procedure; weighted scan enable signals; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Design methodology; Flip-flops; Logic testing; Test pattern generators; Timing; Random testability; scan enable signal; scan-based BIST; weighted random testing;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2007.70767
Filename :
4358224
Link To Document :
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