A high-speed 128-kb MRAM core for future universal memory applications

Author

DeBrosse, John ; Gogl, Dietmar ; Bette, Alexander ; Hoenigschmid, Heinz ; Robertazzi, Raphael ; Arndt, Christian ; Braun, Daniel ; Casarotto, D. ; Havreluk, R. ; Lammers, Stefan ; Obermaier, Werner ; Reohr, William R. ; Viehmann, H. ; Gallagher, William J

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

Volume

39

Issue

4

fYear

2004

fDate

4/1/2004 12:00:00 AM

Firstpage

678

Lastpage

683

Abstract

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-μm V_DD=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-μm² one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.

Keywords

magnetic storage; random-access storage; 0.18 micron; 1.8 V; 128 kbit; 5 ns; MRAM core; circuit assessments; complementary reference cells; configurable load devices; copper metallization; logic process technology; magnetic random access memory; one-transistor one-magnetic tunnel junction cell; random array read access time; random write operations; symmetrical high-speed sensing architecture; test chip; universal memory applications; write pulse width; Circuit testing; Extrapolation; Logic devices; Logic testing; Magnetic cores; Metallization; Pulse measurements; Random access memory; Semiconductor device measurement; Time measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.825251

Filename

1278587