DocumentCode
940764
Title
Convergence behaviour of the first-order multisampling digital tanlock loop
Author
Cho, W.D. ; Un, C.K.
Author_Institution
Korea Advanced Institute of Science and Technology, Communications Research Laboratory, Department of Electrical Engineering, Seoul, South Korea
Volume
135
Issue
5
fYear
1988
fDate
10/1/1988 12:00:00 AM
Firstpage
457
Lastpage
460
Abstract
The convergence behaviour of the first-order multisampling digital tanlock loop (MSDTL) with phase and frequency step inputs is investigated. The MSDTL yields extended locking range, and reduced steady-state mean and variance of phase error as compared with a conventional DTL. It is shown that as the number of samples taken in one period of the received signal increases, the convergence time of the first-order MSDTL decreases sharply.
Keywords
digital circuits; phase-locked loops; convergence behaviour; convergence time; first-order tanlock loop; frequency step inputs; locking range; multisampling digital tanlock loop; period; phase error; phase step input; received signal; steady-state mean; steady-state variance;
fLanguage
English
Journal_Title
Communications, Radar and Signal Processing, IEE Proceedings F
Publisher
iet
ISSN
0143-7070
Type
jour
DOI
10.1049/ip-f-1.1988.0053
Filename
4647507
Link To Document