Evaluation of some proposed name-space architectures using ISPS

In name-space architectures, the mapping of names onto fast registers is a hardware, rather than a software, function. The MU5 computer is an example of such an architecture, having a single-address instruction format with some stacking facilities, and this paper introduces proposed two-store-address and three-store-address architectures developed from MU5 concepts. ISPS descriptions of all three architectures have been written, verified and used in a series of experiments conducted at Carnegie-Mellon University, Pittsburgh, from Manchester University, England, using the ARPA Network. Results are presented of measurements of static and dynamic code usage for a number of benchmark programs run on the ISPS simulation models of these systems, and comparisons between the three architectures are made on the basis of these results.