Low-error carry-free fixed-width multipliers with low-cost compensation circuits

In this paper, we propose a low-error fixed-width redundant multiplier design. The design is based on the statistical analysis of the error compensation value of the truncated partial products in binary signed-digit representation with modified Booth encoding. The overall truncation error is significantly reduced compared with other previous approaches. Furthermore, the derived relationship between the compensation value and the truncated digits is so simple that the area cost of the corresponding compensation circuit is almost negligible. The fixed-width multiplier design is also applied to the discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) computation in JPEG image compression.