Title :
Packet-switched on-chip interconnection network for system-on-chip applications
Author :
Lee, Se-Joong ; Lee, Kangmin ; Song, Seong-Jun ; Yoo, Hoi-Jun
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
fDate :
6/1/2005 12:00:00 AM
Abstract :
Increasing complexity of a system-on-chip design demands efficient on-chip interconnection architecture such as on-chip network to overcome limitations of bus architecture. In this brief, we propose a packet-switched on-chip interconnection network architecture, through which multiple processing units of different clock frequencies can communicate with each other without global synchronization. The architecture is analyzed in terms of area and energy consumption, and implementation issues on building blocks are addressed for cost-effective design. A test chip is implemented using 0.38-μm CMOS technology, and measured its operation at 800 MHz to demonstrate its feasibility.
Keywords :
CMOS integrated circuits; multiprocessor interconnection networks; packet switching; system-on-chip; 0.38 micron; 800 mHz; bus architecture; clock frequency; communication architecture; energy consumption; multiple processing units; on-chip interconnection network; on-chip network; packet switching; system on chip; CMOS technology; Clocks; Computer architecture; Energy consumption; Frequency synchronization; Multiprocessor interconnection networks; Network-on-a-chip; Semiconductor device measurement; System-on-a-chip; Testing; Communication architecture; interconnection network; network on chip (NoC); on-chip network (OCN); system on chip (SoC);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2005.848972
