• DocumentCode
    942083
  • Title

    Adaptively designed test logic for digital circuits

  • Author

    Aleksander, I. ; Al-Bandar, Z.

  • Author_Institution
    Brunel University, Department of Electrical Engineering & Electronics, Uxbridge, UK
  • Volume
    13
  • Issue
    16
  • fYear
    1977
  • Firstpage
    466
  • Lastpage
    467
  • Abstract
    Adaptive n-tuple pattern-recognition techniques in their hardware embodiment may be used to design test circuits for logic systems which indicate the presence of a fault. The principles of this concept are explained and early results obtained with realistically scaled circuits are presented.
  • Keywords
    digital circuits; logic testing; pattern recognition; adaptive n-tuple pattern recognition techniques; digital circuits; test logic;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19770336
  • Filename
    4240454
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=942083