Synthesis of some partially symmetric Boolean functions by ternary algebra

A Boolean function of 2n arguments f(x,y) endowed with the partial symmetries x1~y1 may be described by a binary function ¿(w) of n ternary variables w1 = x1 + y1. The resulting synthesis yields a 4-level design of a circuit computing f(x, y). The method is applied to the design of a b.c.d. adder-convertor.