Title :
An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes
Author :
Vasic, Bane ; Chilappagari, Shashi Kiran
Author_Institution :
Univ. of Arizona, Tucson
Abstract :
In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memory architectures. Our approach is a modification of the method developed by Taylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzero computational (storage) capacity, i.e., the redundancy necessary to ensure reliability grows asymptotically linearly with the memory size. The restoration phase in the TK method is based on low-density parity-check codes which can be decoded using low complexity decoders. The equivalence of the restoration phase in the TK method and faulty Gallager B algorithm enabled us to establish a theoretical framework for solving problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.
Keywords :
fault tolerance; integrated circuit design; integrated circuit reliability; memory architecture; network analysis; parity check codes; information theoretical framework; low-density parity-check codes; memory architecture; memory systems; nanoscale fault-tolerant memories analysis; nanoscale fault-tolerant memories design; nonzero computational capacity; reliable storage; Faulty gates; LDPC codes; low-density parity-check (LDPC) codes; message passing; reliable storage;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2007.902611