Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing

This paper presents a systematic, power-efficient design methodology for the complex finite state machine (FSM) implementation of H.264/AVC decoding. The proposed FSM orchestrates the decoding steps and predicts the type of incoming codeword based on current FSM states and input symbols. The VLSI realization shows a gate count reduction of 14% and an average power reduction of 37.6% in real-time video decoding. The FSM has been implemented with UMC 130 nm 1P6M CMOS technology, and it consumes 38.3 muW at 1.08 V when running at 20 MHz.