Theoretical analysis and modeling of submicron channel length DMOS transistors

Previous analytical models of the DMOS transistor are inadequate at the shorter gate lengths, and can lead to spurious predictions of DMOS device behavior. To avoid such shortcomings, an improved DMOS model is proposed to better address DMOS performance issues. These include the identification of desirable device operating regimes and the examination of device frequency response. Increases in DMOS gate capacitance, which have previously been demonstrated only by computer simulation and device measurements, are now modeled analytically. Furthermore, in demonstrating the shortcomings of previous DMOS models, a universal condition for current saturation in MOS devices is derived. The derivation and applicability of the universal condition is independent of mobility model