A DLL-Based Variable-Phase Clock Buffer

A variable-phase clock buffer that uses a delay-locked loop (DLL) is presented. The variable-phase clock is achieved by switching the multiphase outputs of the divider in the DLL. The output phase is adjustable in a step of where pi/n is the ratio of two voltage-controlled delay lines in the proposed circuit. The prototype has been fabricated in a 0.18- CMOS process to realize the output phases of 0deg, 90deg, 180deg, and 270deg. The corresponding measured phase error is 3.24deg, 3.46deg, 3.89deg, and 1.94deg, respectively. The measured root-mean-squared jitter is 1.81 ps. The clock buffer consumes 67 mW including I/O circuits from a single 1.8-V supply at 600 MHz.