DocumentCode :
943065
Title :
Performance evaluation of a general framing circuit using two N-stage shift registers
Author :
Lee, P.F. ; Chow, Q.S. ; Chow, P.E.K.
Author_Institution :
Bell-Northern Research, Ottawa, Canada
Volume :
13
Issue :
20
fYear :
1977
Firstpage :
598
Lastpage :
599
Abstract :
A general algorithm is presented for computing the average number of shifts per frame period (A) of a framing circuit which checks for N consecutive data bits for possible framing bit candidacy. A simulation program has also been written to compute A for N between 2 and 8.
Keywords :
data transmission equipment; digital communication systems; digital simulation; shift registers; N-stage shift registers; framing circuit; simulation program;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19770430
Filename :
4240571
Link To Document :
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