Title :
A statistical methodology for wire-length prediction
Author :
Wong, Jennifer L. ; Davoodi, Azadeh ; Khandelwal, Vishal ; Srivastava, Ankur ; Potkonjak, Miodrag
Author_Institution :
Comput. Sci. Dept., Univ. of California, Los Angeles, CA
fDate :
7/1/2006 12:00:00 AM
Abstract :
In this paper, the classic wire-length estimation problem is addressed and a new statistical wire-length estimation approach that captures the probability distribution function of net lengths after placement and before routing is proposed. These types of models are highly instrumental in formalizing a complete and consistent probabilistic approach to design automation and design closure where, along with optimizing the pertinent cost function, the associated prediction error is also considered. The wire-length prediction model was developed using a combination of parametric and nonparametric statistical techniques. The model predicts not only the length of the net using input parameters extracted from the floorplan of a design, but also probability distributions that a net with given characteristics after placement will have a particular length. The model is validated using the learn-and-test and resubstitution techniques. The model can be used for a variety of purposes, including the generation of a large number of statistically sound, and therefore realistic, instances of designs. The net models were applied to the probabilistic buffer-insertion problem and substantial improvement was obtained in net delay after routing (~ 20%) when compared to a traditional bounding box (BBOX)-based buffer-insertion strategy
Keywords :
buffer circuits; circuit CAD; integrated circuit interconnections; integrated circuit modelling; statistical distributions; buffer-insertion problem; design automation; learn-and-test technique; net delay; net models; nonparametric statistical modeling; parametric statistical modeling; probability distribution function; resubstitution technique; statistical wire-length estimation; wire-length prediction; Crosstalk; Data mining; Delay; Design automation; Design optimization; Predictive models; Probability distribution; Routing; Statistical analysis; Wire; Buffer insertion; nonparametric statistical modeling; wire length;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.855885