DocumentCode
943286
Title
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation
Author
Shi, C. J Richard ; Tian, Michael W. ; Guoyong Shi
Author_Institution
Dept. of Electr. Eng., Univ. of Washington, Seattle, WA
Volume
25
Issue
7
fYear
2006
fDate
7/1/2006 12:00:00 AM
Firstpage
1392
Lastpage
1400
Abstract
Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By one-step relaxation, only one Newton-Raphson iteration is performed for each faulty circuit with the dc solution of the good circuit as the initial point, and the approximate solution is used for detecting the fault. The paper shows experimentally and justifies theoretically that approximate dc fault simulation by one-step relaxation can accomplish almost the same fault coverage as exact dc fault simulation. Exact dc fault simulation by adaptive simulation continuation is first to order faulty circuits based on the results of one-step relaxation, and then to use the solution of the previous faulty circuit as the initial point for the Newton-Raphson iteration of the next faulty circuit. Experiments on a set of 29 MCNC Circuit Simulation and Modeling Workshop benchmark circuits show that exact dc fault simulation by adaptive simulation continuation can achieve an average speedup of 4.4 and as high as 15 over traditional stand-alone fault simulation
Keywords
Newton-Raphson method; analogue circuits; circuit simulation; fault simulation; nonlinear network analysis; DC fault simulation; Newton-Raphson iteration; adaptive simulation continuation; analog testing; fault coverage; fault ordering; faulty circuit; nonlinear analog circuits; relaxation simulation; Analog circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Failure analysis; Fault detection; Predictive models; System testing; Analog testing; Newton–Raphson iteration; dc fault simulation; fault coverage; fault ordering; first-order approximation; simulation continuation;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2005.855884
Filename
1634634
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