Title :
On modulus 8 gateless synchronous scalers with J-K flip-flops
Author :
Acha, Jose I. ; Huertas, José L.
Author_Institution :
Univesidad de Sevilla, Sevilla, Spain
fDate :
3/1/1976 12:00:00 AM
Abstract :
The problem of finding optimum assignments for a scaler with cycle length 8 is considered. All the possible gateless implementations are obtained by using a computer-aided search. It solves the question about the existence of such an implementation for modulus 8 synchronous scalers.
Keywords :
Combinational circuits; Costs; Equations; Feedback; Flip-flops; Gold;
Journal_Title :
Proceedings of the IEEE
DOI :
10.1109/PROC.1976.10126
