Title :
An asynchronous logic array for the realisation of logic systems with concurrency
Author_Institution :
Université Paul Sabatier de Toulouse, Laboratoire d´Automatique et d´Analyse des Systÿmes du C.N.R.S., Toulouse, France
Abstract :
An array circuit able to implement any logic system described by a Petri net is presented. It uses a request acknowledge asynchronous functioning mode and constitutes a simplification of a solution proposed by Patil previously.
Keywords :
asynchronous sequential logic; cellular arrays; Petri nets; asynchronous logic array; asynchronous sequential logic; cellular arrays; concurrency logic systems realisation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19780081
