DocumentCode
945774
Title
p+ polysilicon emitters for sub-0.5 μm high-performance p-n-p
Author
Warnock, J. ; Sun, J.Y.C. ; Bhattacharya, Surya
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY
Volume
39
Issue
11
fYear
1992
fDate
11/1/1992 12:00:00 AM
Firstpage
2637
Lastpage
2638
Abstract
Summary form only given. The authors describe the tradeoffs between E-B (emitter-base) junction depth, base width, and device characteristics for high-performance sub-0.5-μm p-n-p designs. Near-ideal p-n-p transistors have been fabricated with emitter widths down to 0.25 μm while maintaining an E-B junction depth close to 60 nm. Further improvements in emitter processing, e.g., poly thickness, interfacial oxygen level, emitter implant, and anneal conditions, will allow thinner base widths to be achieved at these small emitter dimensions for future quarter-micrometer complementary bipolar technologies
Keywords
bipolar integrated circuits; bipolar transistors; integrated circuit technology; 0.25 to 0.5 micron; base width; complementary bipolar technologies; device characteristics; emitter-base junction depth; p-n-p transistors; p+ polysilicon emitters; polycrystalline Si; Chemical vapor deposition; Electrons; Etching; Logic devices; Plasma applications; Plasma chemistry; Plasma temperature; Resistors; Shape control; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.163485
Filename
163485
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