DocumentCode
945904
Title
50 A 1200 Vn-channel IGT
Author
Yilmaz, H. ; Chen, L.-S. ; Van Dell, W.R. ; Benjamin, J. ; Chang, M. ; Owyang, K.
Author_Institution
General Electric Company, Power Electronics Semiconductor Department, Syracuse, USA
Volume
132
Issue
6
fYear
1985
fDate
12/1/1985 12:00:00 AM
Firstpage
261
Lastpage
263
Abstract
A 1200 V n-channel insulated gate transistor (IGT) has been designed and evaluated. To reduce the Miller capacitive coupling of the input and the output terminals during the transient conditions, the terraced gate design has been implemented. As a result, the Miller capacitance is lowered 4¿5 times compared to conventional gate design. Also, the gate pad is placed at the centre of the pellet so that the intrinsic device turnon and turnoff times can be shorter. To prevent current crowding and thermal fatigue around a single emitter pad, a multiple emitter pad design scheme is adopted. The 1200 V n-IGTs have reached up to 114 A latch-up current at 150°C.
Keywords
insulated gate field effect transistors; power transistors; 1200 V; 50 A; COMFET; Miller capacitive coupling; current crowding; feedback capacitance reduction; insulated gate transistor; multiple emitter pad design scheme; n-channel IGT; power devices; terraced gate design; thermal fatigue; transient conditions;
fLanguage
English
Journal_Title
Solid-State and Electron Devices, IEE Proceedings I
Publisher
iet
ISSN
0143-7100
Type
jour
DOI
10.1049/ip-i-1.1985.0058
Filename
4648170
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