Coupled Monte Carlo-energy transport simulation with quasi-three-dimensional temperature analysis for SOI MOSFET

Summary form only given. The authors evaluate a temperature-rise effect in short-channel SOI MOSFET using a device simulator that employs a quasi-3-D temperature analysis together with 2-D coupled Monte-Carlo-energy-transport analysis. It is shown that one can accurately simulate the drain current reduction and the negative output resistance in the saturation region due to the temperature rise in the channel. It is found that the temperature rise is significantly influenced by the layout design rule such as the wiring width, the contact hole size, and the gate-to-contact hole separation. Furthermore, it is revealed that the maximum electron temperature is reduced and consequently the drain breakdown voltage is increased due to the decreased number of hot carriers with higher energy when the temperature rise is taken into account