Josephson junction integrated circuit process with planarized PECVD SiO/sub 2/ dielectric

Author

Barfknecht, A.T. ; Ruby, R.C. ; Ko, H.L. ; Lee, G.S.

Author_Institution

Conductus Inc., Sunnyvale, CA, USA

Volume

3

Issue

1

fYear

1993

fDate

3/1/1993 12:00:00 AM

Firstpage

2201

Lastpage

2203

Abstract

As part of the authors´ efforts to reach very-large-scale integration for Nb Josephson junction circuits, they have developed a process technology that includes plasma-enhanced chemical-vapor-deposited (PECVD) SiO/sub 2/ for all interlayer dielectrics, as well as sacrificial resist etch-back planarization to smooth the surface topology under the trilayer. The simple etch-back planarization process is shown to produce quite smooth surfaces. Since the process includes a redeposition step after the planarization etch, the interlayer dielectric integrity is excellent, and no interlayer shorts were observed for these levels. Several products, including DC superconducting quantum interference devices (SQUIDs), have been manufactured using this process technology, with good results and high yield.<>

Keywords

Josephson effect; SQUIDs; VLSI; anodisation; etching; insulating thin films; niobium; photoresists; plasma CVD; plasma CVD coatings; silicon compounds; superconducting integrated circuits; superconducting junction devices; surface topography; type II superconductors; DC superconducting quantum interference devices; Josephson junction integrated circuit process; Nb junction; SiO/sub 2/ interlayer dielectric; anodisation; digital circuits; planarised PECVD dielectric; sacrificial resist etch-back planarization; surface topology; very-large-scale integration; Chemical technology; Dielectrics; Etching; Integrated circuit technology; Josephson junctions; Niobium; Planarization; Plasma applications; SQUIDs; Very large scale integration;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.233940

Filename

233940