Josephson junction integrated circuit process with planarized PECVD SiO/sub 2/ dielectric

As part of the authors´ efforts to reach very-large-scale integration for Nb Josephson junction circuits, they have developed a process technology that includes plasma-enhanced chemical-vapor-deposited (PECVD) SiO/sub 2/ for all interlayer dielectrics, as well as sacrificial resist etch-back planarization to smooth the surface topology under the trilayer. The simple etch-back planarization process is shown to produce quite smooth surfaces. Since the process includes a redeposition step after the planarization etch, the interlayer dielectric integrity is excellent, and no interlayer shorts were observed for these levels. Several products, including DC superconducting quantum interference devices (SQUIDs), have been manufactured using this process technology, with good results and high yield.<>