• DocumentCode
    946448
  • Title

    Realisation of three-valued c.m.o.s. cycling gates

  • Author

    Carmona, J.M. ; Huertas, Jose Luis ; Acha, J.I.

  • Author_Institution
    Universidad de Sevilla, Dpto. de Electricidad y Electrónica, Facultad de Ciencias, Sevilla, Spain
  • Volume
    14
  • Issue
    9
  • fYear
    1978
  • Firstpage
    288
  • Lastpage
    290
  • Abstract
    A new design technique for three-valued cycling operators is presented. The new circuits are shown to be simpler than those previously reported.
  • Keywords
    field effect integrated circuits; integrated logic circuits; logic gates; ternary logic; inverse cycling gates; logic levels; three valued CMOS cycling gates;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19780196
  • Filename
    4241077
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=946448