Title :
A speedup method of a high-speed direct-coupled Josephson logic gate
Author :
Aoyagi, M. ; Nakagawa, H. ; Kurosawa, I. ; Akoh, H. ; Takada, S.
Author_Institution :
Electrotech. Lab., Ibaraki, Japan
fDate :
3/1/1993 12:00:00 AM
Abstract :
The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connected to (R/sub i/) in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. A speedup of 40% in the gate switching was demonstrated by a logic delay experiment using submicron NbN-MgO-NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.<>
Keywords :
Josephson effect; inductance; logic gates; superconducting junction devices; superconducting logic circuits; switching; 3 ps; Josephson logic gate; direct-coupled; four-junction logic gate; high-speed; minimum logic delay; series inductance; speedup method; submicron NbN-MgO-NbN junction technology; switching mechanism; Circuits; Computer simulation; Critical current density; Delay effects; Delay estimation; Inductance; Josephson junctions; Laboratories; Logic gates; Switches;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
