Title :
An integrable MOS neuristor line
Author :
Kulkarni-Kohli, C. ; Newcomb, R.W.
Author_Institution :
University of Maryland, College Park, MD
Abstract :
An integrable MOS design of a neuristor line simulating the conventional properties is presented, the line requiring as few as two sections to simulate the desired properties. In addition the line is low power while consuming no power during the resting state.
Keywords :
Aluminum; Capacitance; Circuit simulation; Circuit testing; Equivalent circuits; Etching; MOS capacitors; Pulse circuits; Silicon; Voltage;
Journal_Title :
Proceedings of the IEEE
DOI :
10.1109/PROC.1976.10390
