Title :
Breaking the frame-buffer bottleneck with logic-enhanced memories
Author :
Poulton, John ; Eyles, John ; Molnar, Steven ; Fuchs, Henry
Author_Institution :
Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
Abstract :
Logic-enhanced memory chips that can remove the rasterizer/frame buffer bottleneck which limits the performance of current image-generation architectures are discussed. Putting pixel memory on-chip with rasterizing processors provides the two to three orders of magnitude improvement in access rates needed to support realistic shading models and aliasing in interactive systems. Current high-performance graphics systems and logic-enhanced memory architectural issues are reviewed. The design of the PixelFlow Enhanced Memory Chip (EMC), which exploits advances in semiconductor technology and circuit techniques to build compact, high-performance rasterizers, is described.<>
Keywords :
DRAM chips; buffer storage; computer graphic equipment; digital signal processing chips; rendering (computer graphics); EMC; PixelFlow Enhanced Memory Chip; aliasing; frame-buffer bottleneck; image-generation architectures; interactive systems; logic-enhanced memories; pixel memory; rasterizing processors; realistic shading models; rendering; semiconductor technology; Bandwidth; Buffer storage; Engines; Geometry; Graphics; Layout; Neck; Pipelines; Random access memory; Read-write memory;
Journal_Title :
Computer Graphics and Applications, IEEE
