DocumentCode :
948966
Title :
Development of a two-step electroplating process with a long-term stability for applying to Cu metallization of 0.1-μm generation logic ULSIs
Author :
Arita, Koji ; Ito, Nobukazu ; Hosoi, Nobuki ; Myamoto, H.
Author_Institution :
ULSI Device Dev. Div., NEC Corp., Sagamihara, Japan
Volume :
15
Issue :
4
fYear :
2002
fDate :
11/1/2002 12:00:00 AM
Firstpage :
493
Lastpage :
496
Abstract :
Developed a two-step copper (Cu) electroplating (EP) process using a seed-enhancement step with an alkali-metal-free Cu-pyrophosphate solution. The solution for the seed-enhancement step has low solubility of Cu compared with conventional Cu-sulfate solution and high macrothrowing power. As a result, the two-step EP solution provided a superior seed-enhancement effect and filling properties compared to conventional Cu sulfate EP. The seed-enhancement solution has excellent long-term stability of each component´s concentration, and there is no change of process performance over a two-month period. The authors can easily control sheet resistance (Rs) of electroplated films which correlates with thickness and nonuniformity of seed-enhancement films with no maintenance other than the addition of de-ionized (DI) water to compensate for evaporated water. The two-step EP process achieved an excellent via-chain yield and a tight distribution of electromigration (EM) lifetime compared with the conventional EP process. Thus, the two-step EP process is a promising process for manufacturing technique of 0.1-μm generation and beyond logic LSIs.
Keywords :
ULSI; copper; electromigration; electroplating; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; process monitoring; 0.1 micron; de-ionized water; electromigration lifetime; filling properties; logic ULSIs; long-term stability; macrothrowing power; metallization; process performance; seed-enhancement step; sheet resistance; solubility; two-step electroplating process; via-chain yield; Atherosclerosis; Copper; Electromigration; Filling; Indium tin oxide; Logic circuits; Metallization; Stability; Thickness control; Ultra large scale integration;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2002.804886
Filename :
1134166
Link To Document :
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