Title :
Propagation delay optimisation in multistage GaAs m.e.s.f.e.t. combinational logic circuits by use of dynamic programming
Author_Institution :
Hewlett-Packard Laboratories, Palo Alto, USA
Abstract :
Propagation delays in multistage combinational logic circuits using GaAs metal-semiconductor field-effect transistors (m.e.s.f.e.t.s) are optimised subject to constraints on the overall power dissipation. Specific optimisation criteria are derived for 1-stage, 2-stage, and 3-stage combinational logic circuits. The results are evaluated with parameters of an existing process.
Keywords :
III-V semiconductors; Schottky gate field effect transistors; circuit CAD; combinatorial circuits; dynamic programming; gallium arsenide; logic gates; GaAs MESFETs; dynamic programming; logic gate propagation delay; multistage combinational logic circuits; optimisation criteria; overall power dissipation; propagation delays optimisation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19790105
