• DocumentCode
    949797
  • Title

    SEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design

  • Author

    Hirose, K. ; Saito, H. ; Kuroda, Y. ; Ishii, S. ; Fukuoka, Y. ; Takahashi, D.

  • Author_Institution
    Inst. of Space & Astron. Sci., Kanagawa, Japan
  • Volume
    49
  • Issue
    6
  • fYear
    2002
  • fDate
    12/1/2002 12:00:00 AM
  • Firstpage
    2965
  • Lastpage
    2968
  • Abstract
    We fabricate 128 Kbit SRAMs using a rad-hard circuit design based on a mixed-mode three-dimensional simulation in a commercial silicon-on-insulator foundry with 0.2 μm design rules. Appropriate design increases the critical linear energy transfer of single-event upset over 164.4 MeV/(mg/cm2).
  • Keywords
    SRAM chips; radiation hardening (electronics); silicon-on-insulator; 0.2 mm; 128 Kbit; SEU resistance; SOI SRAM; fabrication technology; linear energy transfer; mixed-mode three-dimensional simulation; rad-hard circuit design; silicon-on-insulator foundry; Circuit simulation; Circuit synthesis; Energy exchange; Immune system; MOSFETs; Radiation hardening; Silicon on insulator technology; Single event upset; Space technology; Substrates;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2002.805978
  • Filename
    1134247
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=949797