Title :
Asynchronous rate divider and multiplier designs for LEDR logic
Author :
Traver, C. ; Harden, J.C. ; Goodjohn, K. ; Reese, R.B.
Author_Institution :
Electr. & Comput. Eng. Dept., Union Coll., Schenectady, NY, USA
fDate :
4/1/2004 12:00:00 AM
Abstract :
Designs for asynchronous circuit modules that allow communication using level encoded dual-rail (LEDR) signalling between two circuits that operate at different computation rates are presented. Signal transition graphs and asynchronous flow tables are used to design these circuits to the gate and transistor level and they are simulated to validate functionality.
Keywords :
Petri nets; asynchronous circuits; dividing circuits; integrated circuit design; logic design; multiplying circuits; signal flow graphs; asynchronous circuit modules; asynchronous flow tables; asynchronous rate divider; level encoded dual rail signalling; multiplier designs; signal transition graphs;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20040303
