Design of a residue arithmetic multiplier

The design of a pipelined residue-arithmetic multiplier is presented. The design uses multiple radices coded in binary. The multiplier accepts two 8-bit unsigned binary numbers and returns a 16-bit binary product. The five radices 7, 8, 11, 13 and 15, are chosen in a manner to give redundancy to numbers represented in residue arithmetic. This redundancy gives the multiplier an error-detection capability. The layout for the multiplier is implemented in 2.5 μm CMOS and simulation results indicate that the multiplier is capable of operating at 20 MHz