Some aspects of time-division data switch design

A number of techniques for configuring circuit switching data network carrying mixed bearer rate traffic are discussed. In the network, blocking probability unbalance among different bearer rates arises on highway and switch, for example, due to fractional occupation of usable channel for high bearer rate call by lower bearer rate call. Such a problem due to handling mixed bearer rate traffic is first described. Several solutions to this problem are presented and evaluated in terms of memory amount, delay time through switch, and dynamic program steps required for path search procedure. This paper concludes that single-stage time-division switch (T switch) is suitable for data purpose, so far as switch size is relatively small. Also presented are fundamental techniques for designing a T switch with reduced memory chips and reduced memory speed requirement. T switch configuration varieties based on these techniques are quantitatively evaluated. A design method for the most economical and flexible T switch under conditions such as usable memory, traffic distribution in data speed, and local network configuration, is established.