Title :
A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures
Author :
Niu, Guofu ; Krithivasan, Ramkumar ; Cressler, John D. ; Riggs, Pamela A. ; Randall, Barbara A. ; Marshall, Paul W. ; Reed, Robert A. ; Gilbert, Barry
Author_Institution :
Electr. & Comput. Eng. Dept., Auburn Univ., AL, USA
fDate :
12/1/2002 12:00:00 AM
Abstract :
The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications.
Keywords :
Ge-Si alloys; bipolar logic circuits; flip-flops; heterojunction bipolar transistors; high-speed integrated circuits; radiation hardening (electronics); semiconductor materials; D flip-flop circuit; SiGe; bipolar NAND gate; circuit simulation; current sharing hardened circuit; device simulation; emitter coupled pair; high-speed SiGe heterojunction bipolar transistor digital logic design; multiple circuit architecture; single-event upset; space electronics; transistor-level cross-coupling; Circuit simulation; Coupling circuits; Flip-flops; Germanium silicon alloys; Heterojunction bipolar transistors; Logic circuits; Logic design; Logic devices; Silicon germanium; Single event upset;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2002.805390
