An STS-N byte-interleaving multiplexer/scrambler and demultiplexer/descrambler architecture and its experimental OC-48 implementation

Author

Bagheri, Mehran ; Kong, Dennis T. ; Holden, Wayne S. ; Irizarry, Fernando C. ; Mahoney, Derek D.

Author_Institution

Bellcore, Red Bank, NJ, USA

Volume

1

Issue

3

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

282

Lastpage

285

Abstract

The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10^-14. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies

Keywords

SONET; demultiplexing equipment; multiplexing equipment; optical communication equipment; 2.488 Gbit/s; 9.95 Gbit/s; BER; OC-192; OC-48 experiment; SONET; STS-3c; STS-48; bit error rate; byte demultiplexer/descrambler; byte multiplexer/scrambler; byte-interleaving architecture; digital hierarchy; higher order signal generation; interfaces; synchronous optical network; system performance; B-ISDN; Bit error rate; Bit rate; Circuit testing; Helium; Multiplexing; SONET; Signal generators; Standards development; System performance;

fLanguage

English

Journal_Title

Networking, IEEE/ACM Transactions on

Publisher

ieee

ISSN

1063-6692

Type

jour

DOI

10.1109/90.234850

Filename

234850