An optimum CMOS switched-capacitor antialiasing decimating filter

Author

Martins, R.P. ; Franca, José E. ; Maloberti, Franco

Author_Institution

Fac. of Sci. & Technol., Macau Univ., Macau

Volume

28

Issue

9

fYear

1993

fDate

9/1/1993 12:00:00 AM

Firstpage

962

Lastpage

970

Abstract

An optimum switched-capacitor (SC) decimating filter is capable of achieving a high input sampling frequency while the time period for the setting of the operational amplifiers can be maximized with respect to the lower output sampling frequency. Thus, for the same speed of the operational amplifiers, the oversampling ratio of the input signal in optimum SC decimating filters is much larger than in conventional SC filtering circuits, yielding a significant relaxation of the continuous-time prefiltering requirements. This is demonstrated by considering the design of a second-order SC antialiasing decimating filter with a threefold sampling rate reduction, which has been realized in a 1.8-μm CMOS double-poly technology. The experimental evaluation of prototype samples confirms the expected operation of the circuit

Keywords

CMOS integrated circuits; linear integrated circuits; operational amplifiers; switched capacitor filters; 1.8 micron; CMOS; SC filtering circuits; antialiasing decimating filter; double-poly technology; op amp based filter; operational amplifiers; oversampling ratio; sampling rate reduction; switched-capacitor; CMOS technology; Filtering; Filters; Frequency; Operational amplifiers; Prototypes; Sampling methods; Signal sampling; Switching circuits; Video signal processing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.236176

Filename

236176